1. Technical Field
The present invention relates in general to on-chip ECC systems for DRAMs, and more specifically to an interlocked on-chip ECC system that minimizes access delays imposed by the ECC system.
2. Background Art
From the very early stages of DRAM development in the 1970's, designers have recognized the need for some sort of on-chip error recovery circuitry. That is, given the large number of processing steps needed to make a memory chip, and given the large number of discrete transistor-capacitor memory cells to be fabricated, from a practical standpoint it is inevitable that at least some memory cells will not function properly. In the past, this problem was addressed by including spare (or "redundant") rows and/or columns of memory cells, and switching the redundant rows/columns for any rows/columns of the memory array that are faulty.
However, it has become clear that redundancy in and of itself cannot efficiently rectify all of the possible errors that may occur during DRAM operation. Specifically, a memory cell that initially operates properly may operate improperly once it is in use in the field. This may be either a so-called "soft error" (e.g. a loss of stored charge due to an alpha particle radiated by the materials within which the memory chip is packaged) or a "hard error" (a cycle-induced failure in the metallization or other material in the chip that occurs after prolonged use in the field). Because both of these types of errors occur after initial testing, they cannot be corrected by redundancy. Moreover, as the number of rows/columns of cells in the memory increases, the relative fault coverage afforded by each redundant line decreases. These problems have been addressed by the use of error correction codes (ECC) such as Hamming codes or horizontal-vertical (H-V) parity. For a general overview of Hamming codes, see C. Chen et al, "Error Correcting Codes For Semiconductor Memory Applications: A State-of-the-Art Review," IBM Journal of Research and Development, Vol. 28, No. 2, March, 1984 pp. 124-134. In H-V parity, a parity bit for each row and column of a matrix of cells is generated and used for correction. ECC techniques are typically used in larger computer systems wherein data is read out in the form of multi-bit words. While this type of system-level ECC is now being used in smaller systems, it still adds a degree of both logic complexity and expense (due to added circuit cost and decreased data access speed) that makes it infeasible for less complicated systems. In these applications, memory performance/reliability suffers because there is no system-level ECC to correct for errors that occur after initial test.
The solution to this problem is to incorporate ECC circuitry onto the memory chip itself. This reduces the expense associated with ECC, while at the same time increasing the effective memory performance. U.S. Pat. No. 4,335,459, entitled "Single Chip Random Access Memory With Increased Yield and Reliability, " issued Jun. 15, 1982 to Miller, relates to the general idea of incorporating Hamming code ECC on a memory chip. The stored data is read out in ECC words consisting of 12 bits (8 data bits, 4 check bits) that are processed by the ECC circuitry. The corrected 8 data bits are sent to an 8-bit register. The register receives address signals that select one of the 8 bits for output through a single bit I/O.
An article by Gandhi et al, entitled "Dynamic Random-Access Memories With On-Chip Error Checking and Correction," IBM Technical Disclosure Bulletin, October 1984 pp. 2818-19, also discloses the general idea of on-chip ECC, wherein read data is corrected using stored check bits, and wherein new check bits are generated by the ECC system for data to be stored in the DRAM arrays. The ECC system communicates with a static register.
U.S. Pat. No. 4,817,052, entitled "Semiconductor Memory With An Improved Dummy Cell Arrangement And With A Built-In Error Correcting Code Circuit," issued Mar. 28, 1989 to Shinoda et al and assigned to Hitachi, discloses a particular dummy cell configuration as well as the general idea of interdigitating the word lines so that adjacent failing cells on a word line will appear as single-bit fails (and thus be correctable) by the ECC system, because they will appear in different ECC words.
An article by J. Yamada, "Selector-Line Merged Built-In ECC Technique for DRAM's," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October, 1987, pp. 868-873, discloses an on-chip ECC system using H-V parity wherein the assignment of memory cells along a word line to positions within the H-V parity matrix is carried out in a diagonal fashion, such that adjacent cells along the word line are members of different H and V groups. This eliminates long selector lines that couple the cells to their associated H,V parity checkers. This, in combination with a two-tier parity checker, reduces the "possible" access penalty imposed by the on-chip HV parity system to be on the order of 5 nanoseconds. This general system is also disclosed in an article by T. Mano et al, entitled "Circuit Technologies for 16 Mb DRAMs," IEEE International Solid-State Circuits Conference 1987: Digest of Technical Papers, Paper 1.6, pp. 22-23.
An article by T. Yamada et al, entitled "A 4-Mbit DRAM with 16-bit Concurrent ECC," IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, February, 1988 pp. 20-26, discloses an on-chip H-V ECC system in which all of the vertical parities are checked concurrently, eliminating the need for vertical parity selectors. As shown in FIG. 6 of the article, the memory chip passes data from the main sense amplifiers to a set of intermediate amplifiers, and from the intermediate amplifiers to the data latch through column decode switches. The ECC system is coupled in parallel between the intermediate amplifiers and the data output, for correcting the data.
An article by K. Arimoto et al, entitled "A Speed Enhanced DRAM Array Architecture With Embedded ECC, " IEEE Symposium on VLSI Circuits 1989: Digest of Technical Papers, Paper 8-7, discloses a memory arrangement for supporting Hamming code on-chip ECC wherein the memory array consists of a plurality of bit line pairs that are coupled to sub I/O bus lines, which are in turn coupled to main I/O lines via a column decode operation. The bit line data is amplified twice during sensing, such that the main I/O lines (as well as the data register) is provided with amplified logic states. After sensing, the main I/O lines are isolated from the sub I/O bus lines to decrease loading. During the two-stage amplification, the ECC receives data on the sub I/O lines. Because the ECC has a minimum delay, and because it starts operating during the sense cycle, the first data read out in a page access mode cannot be error corrected. However, data read out thereafter is error corrected (see FIG. 5).
An article by M. Asakura et al, entitled "An Experimental 1 Mb Cache DRAM With ECC," IEEE Symposium on VLSI Circuits 1989: Digest of Technical Papers, Paper 4-5, discloses an on-chip SRAM cache for a DRAM supporting on-chip ECC. Accesses between the cache and the DRAM are carried out through the ECC circuitry.
Japanese Published Unexamined Patent Application JP 01-208799, published Aug. 22, 1989 and entitled "Semiconductor Storage Device," apparently relates to a method of shortening the access cycles for on-chip ECC systems. According to the English language abstract obtained from the JAPIO computer database, the patent application teaches the use of a separate high-speed memory array for storing the check bits of an ECC word stored in conventional DRAM arrays. According to the application, the check bits can be obtained faster, such that the total cycle time of the ECC system is reduced.
In several references, both ECC circuitry and redundancy are incorporated on the same memory chip. Examples of such arrangements include U.S. Pat. No. 4,688,219, entitled "Semiconductor Memory Device Having Redundant Memory and Parity Capabilities," issued Aug. 18, 1987 to Takemae and assigned to Fujitsu (bit line redundancy incorporated with HV parity by use of a switching circuit that generates the parity bits for the redundant column line separately from the generation of the parity bits for the remaining cells); U.S. Pat. No. 4,768,193, issued Aug. 30, 1988 to Takemae and assigned to Fujitsu (an array contiguous to the main memory array provides both word line and bit line redundancy for an HV ECC system, wherein fuses are used to disconnect the faulty word line and/or bit line from the horizontal and/or vertical parity generators, respectively); and an article by Furutani et al, "A Built-In Hamming Code ECC Circuit for DRAM's," IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 50-56 (new ECC circuitry for an on-chip Hamming code system, with redundancy--the article does not discuss redundancy in any detail).
As is illustrated in the prior art discussed above, there are a host of known techniques for integrating ECC onto a DRAM chip. It is also clear that there is a wide divergence in the art as to the best way to minimize the access delays imposed by on-chip ECC. In general, the methods used in the art to minimize ECC delays require increased ECC complexity and/or changes to the DRAM data path. Such complexities add design expense and in some cases (e.g. the Arimoto paper) may compromise ECC operation. Accordingly, a need exists in the art for enhancing on-chip ECC performance without introducing such design complexities.